In a data processing system, a direct memory access (DMA) controller is sometimes used to access a memory independently of a central processing unit (CPU). A conventional DMA controller includes its own source and destination registers and an address counter register. The CPU causes initial transfer parameters for a DMA transfer to be loaded in the DMA controller and initiates a DMA transfer of data from a source memory space to a destination memory space. The memory spaces may be either internal or external to the data processing system. The transfer parameters include source and destination addresses, and a counter value. The DMA controller then controls the actual transfer of data, freeing the CPU for other tasks. An entire block of data is usually transferred during each DMA transfer. The size of the block of data is controlled by the counter value.
When a DMA transfer is initiated, the first address to be transferred is provided to the source or destination registers. An address counter register is loaded with the counter value to define the number of address transfers. After each transfer, the address source register or destination register, or both, is incremented and the address counter value is decremented. The transfer is complete when the counter value in the address counter register equals zero. The DMA controller then interrupts the CPU to inform the CPU that the DMA transfer is complete.
In the conventional DMA controller, each time a DMA transfer of data is required, the CPU loads new transfer parameters and initiates the DMA transfer. The CPU is interrupted each time a DMA transfer is complete. As a result, the CPU is involved at both the beginning and the end of each DMA transfer.